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ATmega128
Even though this example is simple, it shows the principles involved in all T W I transmissions.
These can be summarized as follows:
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W hen the T W I has finished an operation and expects application response, the T W INT flag
is set. The SCL line is pulled low until T W INT is cleared.
W hen the T W INT flag is set, the user must update all T W I Registers with the value relevant
for the next T W I bus cycle. As an example, T W DR must be loaded with the value to be
transmitted in the next bus cycle.
After all T W I Register updates and other pending application software tasks have been
completed, T W CR is written. W hen writing T W CR, the T W INT bit should be set. W riting a
one to T W INT clears the flag. The T W I will then commence executing whatever operation
was specified by the T W CR setting.
In the following an assembly and C implementation of the example is given. Note that the code
below assumes that several definitions have been made for example by using include-files.
210
2467X–AVR–06/11
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